1. Field of the Invention
The invention relates to a driving circuit, more particularly to a driving circuit for driving a load, and a pixel circuit that includes the driving circuit for driving an organic light emitting diode.
2. Description of the Related Art
Organic light emitting diode (OLED) displays are increasingly widely used due to the advantages of spontaneous emission of light, high luminance, fast reaction time, and wide viewing angle.
A conventional OLED display utilizes a plurality of pixel circuits that are arranged in matrices and that can emit light of different colors to achieve the function of displaying images. With reference to FIG. 1, each of the pixel circuits includes an organic light emitting diode (OLED) 1 and a first conventional driving circuit 2. The first conventional driving circuit 2 generates a driving current (IDRIVE). The organic light emitting diode 1 is driven by the driving current (IDRIVE) from the first conventional driving circuit 2 to emit light with a luminance that corresponds to a magnitude of the driving current (IDRIVE).
The first conventional driving circuit 2 includes a first transistor 21, a second transistor 22, and a capacitor 23. Each of the first and second transistors 21, 22 is an N-type thin film transistor (TFT), and has a first terminal, a second terminal, and a control terminal.
The organic light emitting diode 1 has a cathode that is adapted to coupling to a first voltage source (VSS). The control terminal of the first transistor 21 is adapted for receiving a scan signal (SCAN). The first terminal of the first transistor 21 is adapted for receiving a data signal (VDATA). The second terminal of the first transistor 21 is coupled electrically to the control terminal of the second transistor 22. The first terminal of the second transistor 22 is adapted for coupling to a second voltage source (VDD). The second terminal of the second transistor 22 is coupled electrically to the second terminal of the first transistor 21 via the capacitor 23, and is coupled electrically to an anode of the organic light emitting diode 1.
Shown in FIG. 2 are timing sequences of the scan signal (SCAN) and the data signal (VDATA) for the first conventional driving circuit 2. When the scan signal (SCAN) is at a logic high level, the first transistor 21 is turned on, such that the data signal (VDATA) is transferred to the control terminal of the second transistor 22, and such that the capacitor 23 stores energy from the data signal (VDATA). On the other hand, when the scan signal (SCAN) is at a logic low level, the first transistor 21 is turned off. The second transistor 22 generates the driving current (IDRIVE) with reference to the energy stored in the capacitor 23 according to the following formula:
      I    DRIVE    =            1      2        ⁢          μ      n        ⁢          C      ox        ⁢                  W        22                    L        22              ⁢                  (                              V                          C              ,              23                                -                      V                          TH              ,              22                                      )            2      where (W22) and (L22) are width and length of the second transistor 22, (VC,23) is the voltage across the capacitor 23, and (VTH,22) is a threshold voltage for the second transistor 22.
Since the threshold voltages of the second transistors 22 for individual pixel circuits are not identical, the driving currents (IDRIVE) generated by the pixel circuits differ from each other even with the same data signal (VDATA), thereby resulting in luminance variations among the light emitted by the organic light emitting diodes 1.
With reference to FIG. 3, in order to diminish the effect of the threshold voltage differences on luminance variations, an article in IEEE ELECTRON DEVICE LETTERS Volume 25, Issue 10, October 2004, and entitled “A New Voltage-Modulated AMOLED Pixel Design Compensation for Threshold Voltage Variation in Poly-Si TFTs” discloses a pixel circuit that incorporates a second conventional driving circuit 2′. The second conventional driving circuit 2′ includes a first transistor 24, a second transistor 25, a third transistor 26, a fourth transistor 27, a fifth transistor 28, and a capacitor 29. Each of the first to fifth transistors 24˜28 is a P-type TFT, and includes a first terminal, a second terminal, and a control terminal. The organic light emitting diode 1 has a cathode that is adapted for coupling to a first voltage source (VSS).
The control terminal of the first transistor 24 is adapted for receiving a scan signal (SCAN). The first terminal of the first transistor 24 is adapted for receiving a data signal (VDATA). The second terminal of first transistor 24 is connected electrically to the first terminals of the second and third transistors 25, 26 and to the control terminal of the third transistor 26 (this node is hereinafter referred to as node (A)). The control terminal of the second transistor 25 is connected electrically to the second terminals of the second and third transistors 25, 26, to the control terminal of the fourth transistor 27, and to one end of the capacitor 29 (this node is hereinafter referred to as node (B)). The first terminal of the fourth transistor 27 is connected electrically to the other end of the capacitor 29, and is adapted for coupling to a second voltage source (VDD). The second terminal of the fourth transistor 27 is connected electrically to the first terminal of the fifth transistor 28. The control terminal of the fifth transistor 28 is adapted for receiving a control signal (CTRL). The second terminal of the fifth transistor 28 is connected electrically to an anode of the organic light emitting diode 1.
Shown in FIG. 4 are timing sequences of the scan signal (SCAN), the data signal (VDATA), and the control signal (CTRL) for the second conventional driving circuit 2′. When the scan signal (SCAN) is at a logic low level, and the control signal (CTRL) is at a logic high level, the first transistor 24 is turned on, and the fifth transistor 28 is turned off, such that the data signal (VDATA) is transferred to the node (A). When the data signal (VDATA) is at a logic low level, the voltage at the node (B) is pulled down by the third transistor 26 until the voltage at the node (B) is equal to the data signal (VDATA) plus the absolute value of the threshold voltage for the third transistor 26. In this situation, the fourth transistor 27 does not generate the driving current (IDRIVE).
When the scan signal (SCAN) is at a logic low level, and the control signal (CTRL) is at a logic low level, the first transistor 24 is turned on, and the fifth transistor 28 is turned on, such that the data signal (VDATA), which is at a logic high level, is transferred to the node (A). At this time, since the data signal (VDATA) is at a logic high level, the voltage at the node (B) is pulled up through the second transistor 25 until the voltage at node (B) is equal to the data signal (VDATA) subtracted by the absolute value of the threshold voltage for the second transistor 25. In this situation, the fourth transistor 27 generates the driving current (IDRIVE) with reference to the voltage across the capacitor 29 according to the following formula:
                              I          DRIVE                =                              1            2                    ⁢                      μ            p                    ⁢                      C            ox                    ⁢                                    W              27                                      L              27                                ⁢                                    (                                                V                                      C                    ,                    29                                                  -                                                                        V                                          TH                      ,                      27                                                                                                    )                        2                                                  =                              1            2                    ⁢                      μ            p                    ⁢                      C            ox                    ⁢                                    W              27                                      L              27                                ⁢                                    (                                                V                  DD                                -                                  V                  B                                -                                                                        V                                          TH                      ,                      27                                                                                                    )                        2                                                  =                              1            2                    ⁢                      μ            p                    ⁢                      C            ox                    ⁢                                    W              27                                      L              27                                ⁢                                    (                                                V                  DD                                -                                  V                  DATA                                +                                                                        V                                          TH                      ,                      25                                                                                        -                                                                        V                                          TH                      ,                      27                                                                                                    )                        2                              where (W27) and (L27) are respectively width and length of the fourth transistor 27, (VC,29) is the voltage across the capacitor 29, (VB) is the voltage at node (B), (VTH,27) is the threshold voltage for the fourth transistor 27, and (VTH,25) is the threshold voltage for the second transistor 25. Since the second and fourth transistors 25, 27 are very close to each other in location, the threshold voltages thereof can be assumed to be identical. Therefore, the formula can be simplified and rewritten as follows.
      I    DRIVE    =            1      2        ⁢          μ      p        ⁢          C      ox        ⁢                  W        27                    L        27              ⁢                  (                              V            DD                    -                      V            DATA                          )            2      
When the scan signal (SCAN) is at a logic high level, and when the control signal (CTRL) is at the logic low level, the first transistor 24 is turned off, and the fifth transistor 28 is turned on. The fourth transistor 27 generates the driving current (IDRIVE) according to the voltage across the capacitor 29.
Since the effect on the driving current (IDRIVE) due to the threshold voltage of the fourth transistor 27 for each of the pixel circuits is canceled out by that due to the threshold voltage of the second transistor 25, the driving currents (IDRIVE) generated by the pixel circuits are identical to each other with the same data signal (VDATA), thereby resulting in identical luminance among the light emitted by the organic light emitting diodes 1.
However, although the second conventional driving circuit 2′ is capable of reducing the effect of the threshold voltage differences on the luminance variations of the organic light emitting diodes 1, three more transistors are required in the second conventional driving circuit 2′ as compared to the first conventional driving circuit 2 (as shown in FIG. 1), thereby reducing an aperture ratio (i.e., a ratio of coverage area of effective illuminating display region) of the OLED display utilizing the second conventional driving circuit 2′. Consequently, utilization efficiency of the light is diminished.